Semiconductor fabrication design rule loophole checking for design for manufacturability optimization
US10585346B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 21, 2017 |
| Grant date | Mar 10, 2020 |
| Priority date | — |
| Expiry date | Nov 21, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.