Tunable on-chip nanosheet resistor
US10586843B2 · kind B2 · utility
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11References
17Claims
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Key dates
| Filing date | Apr 20, 2018 |
| Grant date | Mar 10, 2020 |
| Priority date | — |
| Expiry date | May 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02507
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an integrated circuit device having a nanosheet resistor includes forming a nanosheet structure having alternating sheets of silicon and silicon germanium. An ion implantation is performed on the nanosheet structure. A thermal anneal is performed on the nanosheet structure. A dielectric oxide is placed around the nanosheet structure. A first contact and a second contact are coupled to the nanosheet structure to form a resistor between the first contact and the second contact. Other embodiments are also described herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.