Locked loop circuit with configurable second error input
US10587275B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2018 |
| Grant date | Mar 10, 2020 |
| Priority date | — |
| Expiry date | Dec 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/0014
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A locked loop circuit is disclosed. The locked loop circuit includes phase detection circuitry to generate a first error output based on a phase difference between a first reference input and a locked-loop output. Summing circuitry receives the first error output and a second error signal. The second error signal is based on one from a selection of error values. Oscillator/delay circuitry generates the locked-loop output. For a first mode of operation, the second error signal is based on a first selected error value. For a second mode of operation, the second error signal is based on a second selected error value different than the first selected error value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.