Semiconductor memory device and method of operating a semiconductor device in a processor mode or a normal mode
US10592467B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2017 |
| Grant date | Mar 17, 2020 |
| Priority date | — |
| Expiry date | Apr 21, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/785
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An operation method of a semiconductor memory device including a memory cell array and an internal processor configured to perform an internal processing operation includes receiving at the memory device a first mode indicator that indicates whether the memory device should operate in a processor mode or in a normal mode, receiving at the memory device processing information for the memory device, when the first mode indicator indicates that the memory device should operate in the processor mode, storing the processing information in a first memory cell region of the memory cell array, using the stored processing information to perform internal processing by the internal processor, and storing a result of the internal processing in the memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.