Memory controller with staggered request signal output
US10593379B2 · kind B2 · utility
4Cited by
42References
20Claims
0Family size
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Key dates
| Filing date | Aug 22, 2018 |
| Grant date | Mar 17, 2020 |
| Priority date | — |
| Expiry date | Aug 22, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.