Patent · US Active

Deep fence isolation for logic cells

US10593674B1 · kind B1 · utility

1Cited by

5References

20Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Ming-Cheng Chang · Daxi District, TW
Nigel Chan · Sunnyvale, US
Elliot John Smith · Dresden, DE

Key dates

Filing date	Sep 12, 2018
Grant date	Mar 17, 2020
Priority date	—
Expiry date	Sep 13, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH01L21/76283
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Structures for field-effect transistors and methods for fabricating a structure for field-effect transistors. A logic cell includes first and second field-effect transistors and a well defining a back gate that is arranged beneath the first and second field-effect transistors. A dielectric layer is arranged between the well and the logic cell. A plurality of deep trench isolation regions extend through the dielectric layer and are arranged to surround the first and second field-effect transistors and the well. The back gate is shared by the first and second field-effect transistors.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.