M/A for compiling parallel program having barrier synchronization for programmable hardware
US10599404B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2012 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | Oct 27, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/433
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of compiling program code includes determining if the program code controls a programmable logic device to execute other program code. The program code is a parallel program having a barrier function call for a group of threads. If it is determined that program code is to control the programmable logic device, then the program code is transformed by replacing the barrier function call with control logic inserted into the program code such that the transformed program code remains a parallel program and maintains synchronization among the group of threads. A compiler system that compiles program code with a barrier function call for a group of threads is also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.