Systems and methods for wafer alignment
US10600667B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2019 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | May 23, 2039 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB65G2811/0626
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations. In particular, some embodiments of the present technology determine the center locations of individual vias on a wafer and average them together to obtain an average center location of the set of vias. Based on a comparison of the average center location to a desired center location, the present technology adjusts the wafer position. Additionally, in some embodiments, the present technology compares wafer via patterns to a template and adjusts the position of the wafer based on the comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.