Dynamic interleaver change for bit line failures in NAND flash storage
US10601546B2 · kind B2 · utility
2Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2018 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | Sep 12, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dynamic interleaver performs a read operation to identify bit lines with high failures, and form groups of data bits for parity bits computation, such that each group includes at most one data bit from the bit lines with high failures. Thus, the interleave selects the bit lines with high failures based on a most recent read test, and can be adjusted according to the conditions of the storage device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.