Patent · US Active

Method, system and device for integration of bitcells in a volatile memory array and bitcells in a non-volatile memory array

US10607659B2 · kind B2 · utility

1Cited by

35References

24Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Mudit Bhargava · Austin, US
Shidhartha Das · Cambourne, GB
George McNeil Lattimore · Austin, US
Brian Tracy Cline · Austin, US

Key dates

Filing date	Apr 23, 2018
Grant date	Mar 31, 2020
Priority date	—
Expiry date	Apr 23, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG11C2207/2263
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Disclosed are methods, systems and devices for operation of memory device. In one aspect, volatile memory bitcells and non-volatile memory bitcells may be integrated to facilitate copying of memory states between the volatile and non-volatile memory bitcells.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.