Timing circuit for command path in a memory device
US10607671B2 · kind B2 · utility
1Cited by
1References
15Claims
0Family size
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Key dates
| Filing date | Apr 17, 2018 |
| Grant date | Mar 31, 2020 |
| Priority date | — |
| Expiry date | Apr 20, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus, such as a memory device, that includes circuits and techniques to synchronize various internal signals with an internal clock signal to ensure proper functionality of the memory device. A walk back circuit is provided to mimic propagation delays of an internal command signal, such as a write command signal, and to speed up the delayed internal command signal an amount equivalent to the propagation delays. The walk back circuit includes a mixture of delay elements provided to mimic propagation delays caused by both gate delays and routing delays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.