Memory device
US10607935B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 27, 2018 |
| Grant date | Mar 31, 2020 |
| Priority date | — |
| Expiry date | Feb 27, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device comprises electrode layers stacked in a stacking direction. Semiconductor pillars penetrate the electrode layers in the stacking direction. First wirings are disposed above the plurality of electrode layers at a first level. Each first wiring is electrically connected to a semiconductor pillar. A second wiring is disposed above the plurality of electrode layers at the first level. The second wiring is insulated from semiconductor pillars. The second wiring and the first wirings extend in parallel along a first direction intersecting the stacking direction and are spaced from each other in a second direction. A width of the second wiring the second direction is equal to a width of each first wiring. A spacing distance between the second wiring and a nearest first wiring is greater than a spacing interval between adjacent first wirings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.