Relative frequency offset error and phase error detection for clocks
US10608649B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2018 |
| Grant date | Mar 31, 2020 |
| Priority date | — |
| Expiry date | Nov 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus for providing a clock signal based on a received clock signal includes a time-to-digital converter configured to generate timestamp information based on the received clock signal. The apparatus includes a first filter configured to generate clock period information based on the timestamp information. The apparatus includes a phase monitor circuit. The phase monitor circuit includes a second filter configured to provide a mean period signal of the received clock signal based on the clock period information. The phase monitor includes a phase error detection circuit configured to generate a phase error indicator based on a threshold difference value and a difference between the clock period information and expected clock period information. The expected clock period information is based on the mean period signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.