Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration
US10613754B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2019 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | Oct 9, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06589
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.