Timing analysis for electronic design automation of parallel multi-state driver circuits
US10614182B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Oct 19, 2016 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | Jan 16, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method for manufacturing an integrated circuit chip includes generating a timing model for a first circuit description of an analog parallel multi-state driver circuit. The first circuit description of the analog parallel multi-state driver circuit having programmable driver states. The timing model is dependent on the driver states. The first circuit description of the analog parallel multi-state driver circuit and the generated timing model are provided for insertion into a second circuit description representing a digital system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.