Patterning of high density small feature size pillar structures
US10614867B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2018 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | Jul 31, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1675
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for forming an array of very small pillar structures having a very small feature size that is smaller than the resolution limit of photolithographic process available for patterning such structures. The method involves forming an array of silicon pillar structures over a layer of material that will ultimately form the pillar structures. The array of silicon pillar structures is repeatedly oxidized to form a layer of silicon oxide at an outer surface of the silicon pillar structures and then etched to remove the outer layer of oxide, thereby reducing the features size (i.e. diameter) of the silicon pillar structure. A final oxidation process entirely oxidizes the remaining silicon pillar structures, leaving an array of small silicon oxide pillar structures that can be used as a mask for patterning underlying layers, including the underlying pillar material. The process is especially useful for forming an array of magnetic memory pillars.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.