Memory cell, semiconductor integrated circuit device, and method for manufacturing semiconductor integrated circuit device
US10615168B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2019 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | Aug 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory cell includes a memory gate structure, a first select gate structure, and a second select gate structure. In the memory gate structure, a lower memory gate insulating film, a charge storage layer, an upper memory gate insulating film, and a metal memory gate electrode are stacked in this order. The first select gate structure includes a metal first select gate electrode along a first sidewall spacer provided on a sidewall of the memory gate structure. The second select gate structure includes a metal second select gate electrode along a second sidewall spacer provided on another sidewall of the memory gate structure. Thus, the metal memory gate electrode, the metal first select gate electrode, and the metal second select gate electrode can be formed of a same metallic material as a metal logic gate electrode, permitting the memory cell to be formed together with the metal logic gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.