Nonvolatile charge trap memory device having a high dielectric constant blocking region
US10615289B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2016 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | Aug 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An embodiment of a nonvolatile charge trap memory device is described. In one embodiment, the device comprises a channel comprising silicon overlying a surface on a substrate electrically connecting a first diffusion region and a second diffusion region of the memory device, and a gate stack intersecting and overlying at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a split charge-trapping region abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the split charge-trapping region. The split charge-trapping region includes a first charge-trapping layer comprising a nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a nitride overlying the first charge-trapping layer. The multi-layer blocking dielectric comprises at least a high-K dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.