Memory device that changes a writable region of a data buffer based on an operational state of an ECC circuit
US10621034B2 · kind B2 · utility
2Cited by
8References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2017 |
| Grant date | Apr 14, 2020 |
| Priority date | — |
| Expiry date | Oct 25, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a semiconductor memory unit, a controller circuit configured to communicate with a host through a serial interface, store write data to be written into a page of the semiconductor memory unit in a data buffer, and an error-correcting code (ECC) circuit configured to generate an error correction code from the write data if the ECC circuit is enabled. The controller circuit writes the error correction code with the write data into the page if the ECC circuit is enabled. A maximum column address of the page which is accessible from the host changes depending on whether or not the ECC circuit is enabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.