Final passivation for wafer level warpage and ULK stress reduction
US10622319B2 · kind B2 · utility
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12References
7Claims
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Key dates
| Filing date | Jul 6, 2017 |
| Grant date | Apr 14, 2020 |
| Priority date | — |
| Expiry date | Nov 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/35121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.