Ekta Misra
22Patents
4h-index
23Co-inventors
59Inventor score
Filing activity: Aug 18, 2005 → Jun 12, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8937009B2 | Far back end of the line metallization method and structures | Electricity | 6 | Active |
| US8492892B2 | Solder bump connections | Electricity | 4 | Active |
| US8563416B2 | Coaxial solder bump support structure | Electricity | 4 | Active |
| US8298929B2 | Offset solder vias, methods of manufacturing and design structures | Emerging Cross-Sectional Technologies | 4 | Active |
| US9754905B1 | Final passivation for wafer level warpage and ULK stress reduction | Electricity | 4 | Active |
| US9159696B2 | Plug via formation by patterned plating and polishing | Electricity | 4 | Active |
| US10090271B1 | Metal pad modification | Electricity | 3 | Active |
| US8778792B2 | Solder bump connections | Electricity | 3 | Active |
| US7446037B2 | Cladded silver and silver alloy metallization for improved adhesion and electromigration resistance | Electricity | 3 | Active |
| US8299581B2 | Passivation layer extension to chip edge | Electricity | 3 | Active |
| US7888263B2 | Cladded silver and silver alloy metallization for improved adhesion electromigration resistance | Electricity | 2 | Active |
| US8446006B2 | Structures and methods to reduce maximum current density in a solder ball | Electricity | 2 | Active |
| US10373925B2 | Metal pad modification | Electricity | 1 | Active |
| US9214385B2 | Semiconductor device including passivation layer encapsulant | Electricity | 0 | Active |
| US9842810B1 | Tiled-stress-alleviating pad structure | Electricity | 0 | Active |
| US9633962B2 | Plug via formation with grid features in the passivation layer | Electricity | 0 | Active |
| US10593639B2 | Metal pad modification | Electricity | 0 | Active |
| US9431359B2 | Coaxial solder bump support structure | Electricity | 0 | Active |
| US11756911B2 | Metal pad modification | Electricity | 0 | Active |
| US10622319B2 | Final passivation for wafer level warpage and ULK stress reduction | Electricity | 0 | Active |
| US8674506B2 | Structures and methods to reduce maximum current density in a solder ball | Electricity | 0 | Active |
| US10096557B2 | Tiled-stress-alleviating pad structure | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.