Inventor · Wappingers Falls, NY, US

Krishna R. Tunga

44Patents
3h-index
42Co-inventors
59Inventor score

Filing activity: Jun 27, 2011 → Oct 18, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US9754905B1 Final passivation for wafer level warpage and ULK stress reduction Electricity 4 Active
US10916154B2 Language learning and speech enhancement through natural language processing Physics 3 Active
US10090271B1 Metal pad modification Electricity 3 Active
US8592970B2 Multichip electronic packages and methods of manufacture Electricity 2 Active
US10325830B1 Multipart lid for a semiconductor package with multiple components Electricity 1 Active
US10665524B2 Electronic package cover having underside rib Electricity 1 Active
US9563732B1 In-plane copper imbalance for warpage prediction Physics 1 Active
US11302651B2 Laminated stiffener to control the warpage of electronic chip carriers Electricity 1 Active
US10276534B2 Reduction of solder interconnect stress Electricity 1 Active
US10541211B2 Control warpage in a semiconductor chip package Electricity 1 Active
US10424527B2 Electronic package with tapered pedestal Electricity 1 Active
US10373925B2 Metal pad modification Electricity 1 Active
US11210968B2 Behavior-based interactive educational sessions Physics 1 Active
US10426400B2 Optimized individual sleep patterns Human Necessities 1 Active
US11282773B2 Enlarged conductive pad structures for enhanced chip bond assembly yield Electricity 1 Active
US9865557B1 Reduction of solder interconnect stress Electricity 1 Active
US8860206B2 Multichip electronic packages and methods of manufacture Electricity 0 Active
US10756031B1 Decoupling capacitor stiffener Electricity 0 Active
US10777482B2 Multipart lid for a semiconductor package with multiple components Electricity 0 Active
US10249548B2 Test cell for laminate and method Electricity 0 Active
US10636746B2 Method of forming an electronic package Electricity 0 Active
US10108753B2 Laminate substrate thermal warpage prediction for designing a laminate substrate Physics 0 Active
US10096557B2 Tiled-stress-alleviating pad structure Electricity 0 Active
US9947598B1 Determining crackstop strength of integrated circuit assembly at the wafer level Electricity 0 Active
US10832987B2 Managing thermal warpage of a laminate Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.