System and method for manufacturing self-aligned STI with single poly
US10622370B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2015 |
| Grant date | Apr 14, 2020 |
| Priority date | — |
| Expiry date | Sep 25, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.