Magnetic memory cell and fabrication method thereof
US10622407B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2019 |
| Grant date | Apr 14, 2020 |
| Priority date | — |
| Expiry date | Aug 20, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/155
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A magnetic memory cell includes a substrate having a memory region, a transistor within the memory region, a first dielectric layer disposed on the substrate, a landing pad in the first dielectric layer, a second dielectric layer covering the first dielectric layer and the landing pad, a cylindrical memory stack in the second dielectric layer, and a source line in the first dielectric layer. The first dielectric layer covers the memory region and the transistor. The landing pad is situated in a first horizontal plane and is coupled to a drain region of the transistor. The cylindrical memory stack has a bottom electrode connected to the landing pad and a top electrode electrically connected to a bit line. The source line is situated in a second horizontal plane and is connected to a source region of the transistor. The second horizontal plane is lower than the first horizontal plane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.