FinFET semiconductor device with a dummy gate, first gate spacer and second gate spacer
US10622444B2 · kind B2 · utility
2Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2018 |
| Grant date | Apr 14, 2020 |
| Priority date | — |
| Expiry date | Sep 7, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
Abstract
A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.