Low latency data transfer technique for mesochronous divided clocks
US10623174B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2018 |
| Grant date | Apr 14, 2020 |
| Priority date | — |
| Expiry date | Dec 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/336
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Electrical circuits and associated methods relate to performing a phase alignment by providing N copies of clock alignment circuits, enabling and selecting different clock alignment circuits to achieve an initial phase alignment. In an illustrative example, a phase alignment circuit may include a first clock alignment circuit configured to find a first phase alignment point and a second clock alignment circuit configured to find a second phase alignment point. A control circuit may be configured to select a primary clock alignment circuit from the first clock alignment circuit and the second clock alignment circuit and generate a digital command signal to control a phase interpolator. In various embodiments, by setting the control circuit, the same phase alignment circuit may be used to perform phase alignments between clock domains with different frequencies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.