Solder resist layers for coreless packages and methods of fabrication
US10629469B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2017 |
| Grant date | Apr 21, 2020 |
| Priority date | — |
| Expiry date | Nov 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19106
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.