Method and structure for forming a vertical field-effect transistor using a replacement metal gate process
US10629499B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2018 |
| Grant date | Apr 21, 2020 |
| Priority date | — |
| Expiry date | Jun 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
Abstract
A method for manufacturing a vertical transistor device includes forming a first plurality of fins in a first device region on a substrate, and forming a second plurality of fins in a second device region on the substrate. In the method, a plurality of dummy gate layers are formed on the substrate and around portions of each of the first and second plurality of fins in the first and second device regions. A barrier layer is formed between the first and second device regions. More specifically, the barrier layer is formed between respective gate regions of the first and second device regions. The method also includes removing the plurality of dummy gate layers from the first and second device regions, and replacing the removed plurality of dummy gate layers with a plurality of gate metal layers in the first and second device regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.