Fabricating method of fin structure with tensile stress and complementary FinFET structure
US10629734B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2019 |
| Grant date | Apr 21, 2020 |
| Priority date | — |
| Expiry date | Jan 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.