Systems and methods for selectively filtering, buffering, and processing cache coherency probes
US10635591B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 2018 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | Dec 5, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods selectively filter, buffer, and process cache coherency probes. A processor includes a probe buffering unit that includes a cache coherency probe buffer. The probe buffering unit receives cache coherency probes and memory access requests for a cache. The probe buffering unit identifies and discards any of the probes that are directed to a memory block that is not cached in the cache, and buffers at least a subset of the remaining probes in the probe buffer. The probe buffering unit submits to the cache, in descending order of priority, one or more of: any buffered probes that are directed to the memory block to which a current memory access request is also directed; any current memory access requests that are directed to a memory block to which there is not a buffered probe also directed; and any buffered probes when there is not a current memory access request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.