Memory device with reduced neighbor word line interference using adjustable voltage on source-side unselected word line
US10636501B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2019 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | Mar 18, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are described for reducing program disturb including neighbor word interference in a memory device. Voltages applied to the word lines adjacent to the selected word line WLn during program and read operations are adjusted. The adjacent word lines include WLn−1, a source-side adjacent word line of WLn, and WLn+1, a drain side adjacent word line of WLn. In one aspect, VWLn−1<VWLn+1 during the verify tests of the program operation for the data states above the lowest programmed data state and VWLn−1=VWLn+1 during the verify test for the lowest programmed data state. Also, VWLn−1<VWLn+1 during a read operation which distinguishes between the programmed data states and VWLn−1=VWLn+1 during a read operation which distinguishes between erased state and the lowest programmed data state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.