Planarization process
US10636671B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 8, 2019 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | Mar 8, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02532
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A planarization process includes the following steps. A first dielectric layer and a second dielectric layer are sequentially formed to conformally cover a pattern in a cell area and a substrate in the cell area and an isolation area, thereby the first dielectric layer and the second dielectric layer having a dishing in the isolation area. A dummy material is formed in the dishing and exposes a part of the second dielectric layer right above the pattern. A first removing process is performed to remove the exposed part of the second dielectric layer. The dummy material is removed. A second removing process is performed to remove an exposed part of the first dielectric layer by using the second dielectric layer as an etch stop layer. A third removing process is performed to remove the second dielectric layer and the first dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.