Metal via processing schemes with via critical dimension (CD) control for back end of line (BEOL) interconnects and the resulting structures

US10636700B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Paul A. Nyhus · Portland, US
• Mohit K. HARAN · Hillsboro, US
• Charles H. Wallace · Portland, US
• Robert M. Bigwood · Hillsboro, US
• Deepak S. Rao · Portland, US
• Alexander F. Kaplan · Portland, US

Key dates

• Filing date: May 3, 2019
• Grant date: Apr 28, 2020
• Expiry date: May 3, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L23/5226
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Via CD control for BEOL interconnects is described. For example, a method of fabricating an interconnect structure includes forming a lower metallization layer comprising alternating metal lines and dielectric lines above a substrate. The method also includes forming an inter-layer dielectric layer above the metallization layer. The method also includes forming a first grating pattern above the inter-layer dielectric layer, orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer. The method also includes forming a second grating pattern above the first grating pattern. The method also includes patterning the inter-layer dielectric layer using the first grating pattern and the second grating pattern to form via locations and line regions in the inter-layer dielectric layer. The method also includes forming metal vias and metal lines in the via locations and line regions, respectively, of the inter-layer dielectric layer.