System and method for SoC power-up sequencing
US10637462B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2019 |
| Grant date | Apr 28, 2020 |
| Priority date | — |
| Expiry date | May 30, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Apparatus and associated methods relate to a consolidated power-on-reset system (PORS) at a system-on-chip (SoC) level. In an illustrative example, an integrated circuit may include a first power domain and a second power region. A level shifter circuit may be coupled to translate data from the first power domain to the second power domain. A PORS including a voltage detection circuit, a glitch filter circuit, and logic gates may be configured to generate isolation signals between the first power domain and the second power domain. The level shifter circuit may be enabled in response to the generated isolation signals. By using the isolation signals, multiple power domains on IC may be managed comprehensively during power-up to avoid unstable operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.