Weiguang Lu
25Patents
7h-index
41Co-inventors
65Inventor score
Filing activity: Sep 23, 2005 → Jul 26, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9722613B1 | Circuit arrangement for and a method of enabling a partial reconfiguration of a circuit implemented in an integrated circuit device | Electricity | 53 | Active |
| US8099625B1 | Self-checking and self-correcting internal configuration port circuitry | Physics | 26 | Active |
| US7218567B1 | Method and apparatus for the protection of sensitive data within an integrated circuit | Electricity | 25 | Expired |
| US8786310B1 | Partially programming an integrated circuit using control memory cells | Electricity | 21 | Active |
| US8058897B1 | Configuration of a multi-die integrated circuit | Electricity | 17 | Active |
| US8438436B1 | Secure design-for-test scan chains | Physics | 10 | Active |
| US10637462B1 | System and method for SoC power-up sequencing | Electricity | 8 | Active |
| US8633730B1 | Power control using global control signal to selected circuitry in a programmable integrated circuit | Emerging Cross-Sectional Technologies | 7 | Active |
| US10305511B1 | Run length compression and decompression using an alternative value for single occurrences of a run value | Physics | 4 | Active |
| US8601306B1 | Decryption of configuration data for multi-die integrated circuits | Electricity | 4 | Active |
| US8635581B1 | Method and apparatus for single event upset (SEU) detection and correction | Physics | 4 | Active |
| US8103919B1 | Circuit for and method of repairing defective memory | Physics | 4 | Active |
| US8713409B1 | Bit error mitigation | Physics | 4 | Active |
| US8922242B1 | Single event upset mitigation | Electricity | 3 | Active |
| US10825541B1 | Built in configuration memory test | Physics | 3 | Active |
| US8384418B1 | Mitigating the effect of single event transients on input/output pins of an integrated circuit device | Electricity | 2 | Active |
| US10108376B1 | Memory initialization | Physics | 2 | Active |
| US8536895B2 | Configuration of a multi-die integrated circuit | Electricity | 2 | Active |
| US9483416B1 | Secure processor operation using integrated circuit configuration circuitry | Physics | 1 | Active |
| US11386009B2 | Programmable device configuration memory system | Physics | 0 | Active |
| US10963170B2 | Retaining memory during partial reconfiguration | Emerging Cross-Sectional Technologies | 0 | Active |
| US10169264B1 | Implementing robust readback capture in a programmable integrated circuit | Physics | 0 | Active |
| US10666266B1 | Configuration engine for a programmable circuit | Electricity | 0 | Active |
| US12148464B2 | Current leakage management controller for reading from memory cells | Electricity | 0 | Active |
| US10763862B1 | Boundary logic interface | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.