Partially de-centralized latch management architectures for storage devices
US10642513B2 · kind B2 · utility
5Cited by
13References
22Claims
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Key dates
| Filing date | Feb 19, 2018 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | Feb 19, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F3/0679
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage device may utilize de-centralized latch management to remove functions from the device controller to the memory die. NAND die located on a common bus may share a pool of latches with one die acting as a proxy or manager for the other die. A bridge or bridges may be used between NAND connections to allow additional die to be controlled by a leader die for the partially de-centralized management of latches. The latch management operations may include a sequence of commands/operations performed by the leader die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.