Processor with an expandable instruction set architecture for dynamically configuring execution resources
US10642617B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2016 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | Jun 4, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor with an expandable instruction set architecture for dynamically configuring execution resources. The processor includes a programmable execution unit (PEU) that may be programmed to perform a user-defined function in response to a user-defined instruction (UDI). The PEU includes programmable logic elements and programmable interconnectors that are collectively programmed to perform at least one processing operation. A UDI loader is responsive to a UDI load instruction that specifies a UDI and a location of programming information that is used to program the PEU. The PEU may be programmed for one or more UDIs for one or more processes. An instruction table stores each UDI and corresponding information to identify the UDI and possibly to reprogram the PEU if necessary. A UDI handler consults the instruction table to identify a received UDI and to send corresponding information to the PEU to execute the corresponding user-defined function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.