Concurrent formal verification of logic synthesis
US10643012B1 · kind B1 · utility
1Cited by
2References
21Claims
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Key dates
| Filing date | Jan 31, 2019 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | Jan 31, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3323
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques and systems for concurrent formal verification of logic synthesis are described. A synthesis tool can write intermediate checkpoint designs that embody the state of an integrated circuit (IC) design under synthesis as optimization progresses. Meanwhile, formal equivalence checking proceeds in parallel with synthesis and checks the intermediate checkpoint designs for equivalence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.