Lisa McIlwain
4Patents
2h-index
14Co-inventors
45Inventor score
Filing activity: Jan 9, 2002 → Aug 25, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6668362B1 | Hierarchical verification for equivalence checking of designs | Physics | 22 | Expired |
| US8650513B2 | Reducing x-pessimism in gate-level simulation and verification | Physics | 4 | Active |
| US10643012B1 | Concurrent formal verification of logic synthesis | Physics | 1 | Active |
| US11526641B2 | Formal gated clock conversion for field programmable gate array (FPGA) synthesis | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.