Compiler-assisted techniques for memory use reduction in graphics pipeline
US10643369B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2018 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | May 30, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2200/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for improving memory utilization for communication between stages of a graphics processing pipeline are disclosed. The techniques include analyzing output instructions of a first shader program to determine whether any such output instructions output some data that is not used by a second shader program. The compiler performs data packing if gaps exist between used output data to reduce memory footprint. The compiler generates optimized output instructions in the first shader program and optimized input instructions in the second shader program to output the used data from the first shader program and input that data in the second shader program in a packed format based on information about usage of output data and data packing. If needed, the compiler inserts instructions to perform runtime checking to identify unused output data of the first shader program based on information not known at compile-time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.