Negative kick on bit line control transistors for faster bit line settling during sensing
US10643677B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 26, 2018 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | Jun 26, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device and associated techniques improve a settling time of bit lines in a memory device during a read or verify operation. Bit line control (BLC) transistors in the sense circuits are briefly turned off during a sensing process. After the read voltage on a selected word line is changed to a second word line level or higher, a control gate voltage of the BLC transistor is lowered. This helps to inhibit a current flow from a sense circuit through a bit line when a voltage of the bit line is settling. The voltage of the bit line may be settling in response to a memory cell coupled to the selected word line undergoing a transition from off to on. A settling time of the bit line is shortened by stopping the current flow from the sense circuit. The transition of the memory cell from off to on is also improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.