Concurrent multi-state program verify for non-volatile memory
US10643695B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2019 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | Jan 10, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sense amplifier for a memory circuit that can sense into the deep negative voltage threshold region is described. A selected memory cell is sensed by discharging a source line through the memory cell into the bit line and sense amplifier. While discharging the source line through the memory cell into the sense amplifier, a voltage level on the discharge path is used to set the conductivity of a discharge transistor to a level corresponding to the conductivity of the selected memory cell. A sense node is then discharged through the discharge transistor. By allowing the sense amplifier to bias a memory cell being sensed to a selected one of multiple bias levels during a sensing operation, multiple target data states can be concurrently program verified, leading to higher performance when writing data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.