Interleaved program and verify in non-volatile memory
US10643721B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2018 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | Jun 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit includes a program controller configured to perform a program operation with interleaved program-verify loops to program memory cells in a same block. During each program-verify loop, a control gate line voltage supply circuit first supplies a program pulse to a first cell of the block and then, before verifying the first cell, supplies a program pulse to a second cell of the block. After the program pulses are sent, the control gate line supply circuit consecutively supplies verify pulses to the first cell and the second cell such that a delay is introduced between the respective program and verify stages of the first and second cells. Additionally, a constant voltage bias on common control gate lines of the first and second memory cells is applied during the consecutive verify stages. Further, an order of verify pulses may be applied in a reverse order during a verify stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.