Self-aligned interconnects formed using subtractive techniques
US10643895B2 · kind B2 · utility
3Cited by
11References
14Claims
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Key dates
| Filing date | Sep 11, 2017 |
| Grant date | May 5, 2020 |
| Priority date | — |
| Expiry date | Sep 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.