Methods, apparatus, and system for reducing gate cut gouging and/or gate height loss in semiconductor devices

US10644156B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Jinsheng Gao · Clifton Park, US
• Daniel Jaeger · Saratoga Springs, US
• Michael V. Aquilino · Wappingers Falls, US
• Patrick Carpenter · Saratoga Springs, US
• Xusheng Wu · Hsinchu, TW
• Haigou Huang · Rexford, US

Key dates

• Filing date: Mar 12, 2018
• Grant date: May 5, 2020
• Expiry date: Mar 12, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/215

Abstract

Methods comprising providing a semiconductor substrate; a fin disposed on the semiconductor substrate; a dummy gate disposed over the fin, wherein the dummy gate has a top at a first height above the substrate; and an interlayer dielectric (ILD) disposed over the fin and adjacent to the dummy gate, wherein the ILD has a top at a second height above the substrate, wherein the second height is below the first height; and capping the ILD with a dielectric cap, wherein the dielectric cap has a top at the first height. Systems configured to implement the methods. Semiconductor devices produced by the methods.