Apparatus for and method of net trace prior level subtraction
US10649026B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2017 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Jun 2, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method in which connectivity tests of integrated circuit structures in a die are performed. The connectivity tests are performed at a first level of the die. Potential defect locations are identified in the die indicating via locations susceptible to systematic failure due to via opens or via shorts. The potential defect locations are translated to via locations for a second level of the die. The second level is below the first level. After translating the hot spot, the second level is inspected for defects. The via locations on the first level are inspected for defects. All defects for the second level are translated to the via locations for the first level. A net trace of defects is created using prior level subtraction of the translated defects for the second level and the defects for the first level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.