Static random access memory with a supplementary driver circuit and method of controlling the same
US10650882B2 · kind B2 · utility
13Cited by
1References
20Claims
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Key dates
| Filing date | Oct 15, 2014 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Oct 15, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory (SRAM) including at least a first memory cell array, a second memory cell array, a first data line connected to the first memory cell array and the second memory cell array, a primary driver circuit connected to the first data line and a supplementary driver circuit connected to the first data line, wherein the supplementary driver circuit is configured to pull a voltage level of the first data line to a first voltage level during a write operation of the SRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.