Post-passivation interconnect structure and method of forming the same
US10651055B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jul 30, 2018 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Jul 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a passivation layer formed on a semiconductor substrate, a protective layer overlying the passivation layer and having an opening, an interconnect structure formed in the opening of the protective layer, a bump formed on the interconnect structure, and a molding compound layer overlying the interconnect structure and being in physical contact with a lower portion of the bump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.