Three-dimensional (3D) memory with shared control circuitry using wafer-to-wafer bonding
US10651153B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2018 |
| Grant date | May 12, 2020 |
| Priority date | — |
| Expiry date | Jun 18, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Wafer-to-wafer bonding is used to form three-dimensional (3D) memory components such as 3D NAND flash memory with shared control circuitry on one die to access arrays on multiple dies. In one example, a non-volatile storage device includes a first die including a 3D array of non-volatile storage cells and CMOS (complementary metal oxide semiconductor) circuitry. A second die including a second 3D array of non-volatile storage cells is vertically stacked and bonded with the first die. At least a portion of the CMOS circuitry of the first die to access both the first 3D array of non-volatile storage cells of the first die and the second 3D array of non-volatile storage cells of the second die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.