Richard Fastow
91Patents
18h-index
89Co-inventors
87Inventor score
Filing activity: Jan 31, 2000 → Mar 28, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7414281B1 | Flash memory with high-K dielectric material between substrate and gate | Electricity | 531 | Expired |
| US6275414A | Uniform bitline strapping of a non-volatile memory cell | Electricity | 111 | Expired |
| US6996004B1 | Minimization of FG-FG coupling in flash memory | Physics | 109 | Expired |
| US6438031B1 | Method of programming a non-volatile memory cell using a substrate bias | Physics | 83 | Expired |
| US6449188B1 | Low column leakage nor flash array-double cell implementation | Physics | 71 | Expired |
| US6252803A | Automatic program disturb with intelligent soft programming for flash cells | Physics | 66 | Expired |
| US6583479B1 | Sidewall NROM and method of manufacture thereof for non-volatile memory cells | Electricity | 49 | Expired |
| US10651153B2 | Three-dimensional (3D) memory with shared control circuitry using wafer-to-wafer bonding | Electricity | 44 | Active |
| US6538270B1 | Staggered bitline strapping of a non-volatile memory cell | Electricity | 37 | Expired |
| US6438037B1 | Threshold voltage compacting for non-volatile semiconductor memory designs | Physics | 36 | Expired |
| US6593606B1 | Staggered bitline strapping of a non-volatile memory cell | Electricity | 35 | Expired |
| US6570211B1 | 2Bit/cell architecture for floating gate flash memory product and associated method | Electricity | 32 | Expired |
| US6285588A | Erase scheme to tighten the threshold voltage distribution of EEPROM flash memory cells | Physics | 28 | Expired |
| US7009271B1 | Memory device with an alternating Vss interconnection | Electricity | 27 | Expired |
| US6452840B1 | Feedback method to optimize electric field during channel erase of flash memory devices | Physics | 25 | Expired |
| US6646914B1 | Flash memory array architecture having staggered metal lines | Physics | 24 | Expired |
| US6363014B1 | Low column leakage NOR flash array-single cell implementation | Physics | 22 | Expired |
| US6937518B1 | Programming of a flash memory cell | Physics | 18 | Expired |
| US7283398B1 | Method for minimizing false detection of states in flash memory devices | Physics | 16 | Expired |
| US7272060B1 | Method, system, and circuit for performing a memory related operation | Physics | 14 | Expired |
| US6477083B1 | Select transistor architecture for a virtual ground non-volatile memory cell array | Physics | 13 | Expired |
| US6510085B1 | Method of channel hot electron programming for short channel NOR flash arrays | Physics | 13 | Expired |
| US6294430A | Nitridization of the pre-ddi screen oxide | Emerging Cross-Sectional Technologies | 13 | Expired |
| US6207978A | Flash memory cells having a modulation doped heterojunction structure | Electricity | 13 | Expired |
| US6750157B1 | Nonvolatile memory cell with a nitridated oxide layer | Electricity | 12 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.